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- return Assembler { opcodes: opcodes }; + Assembler { opcodes: opcodes } } pub fn assemble(&mut self, source: &mut String) -> Vec { @@ -34,7 +34,7 @@ impl Assembler { map.insert(opcode.key.clone(), opcode.value.clone()); } - return Regex::new(r"[\s]+") // create regex + Regex::new(r"[\s]+") // create regex .unwrap() .split(source) // split by regex .filter(|s: &&str| !s.is_empty()) // remove empty entries @@ -56,6 +56,6 @@ impl Assembler { s.parse::().ok() } }) - .collect(); + .collect() } } diff --git a/src/cpu.rs b/src/cpu.rs index 981cd0c..a13286c 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -1,33 +1,71 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // Copyright (c) 2024 Patrick_Pluto +use crate::assembler; + +pub trait CPU { + fn create(debug: bool, initial_state: Vec) -> Self; + fn assemble(source: String) -> Vec; + fn start(&mut self); +} + // This is an example implementation of a CPU emulator. You can copy this for your own custom ISA, or do something else. pub struct ExampleCPU { debug: bool, execution_pointer: u8, operands: [u8; 3], ram: [u8; 256], - registers: [u8; 8], + registers: [u8; 4], } -impl ExampleCPU { +impl CPU for ExampleCPU { // Here is where you can create your own CPU Instance. - pub fn create(debug: bool, initial_state: [u8; 256]) -> ExampleCPU { - return ExampleCPU { - debug: debug, + fn create(debug: bool, initial_state: Vec) -> ExampleCPU { + let mut instance: ExampleCPU = ExampleCPU { + debug, execution_pointer: 0, operands: [0; 3], - ram: initial_state, - registers: [0; 8], + ram: [0; 256], + registers: [0; 4], }; + + let len = initial_state.len(); + let ram_len = instance.ram.len(); + + if len >= ram_len { + instance.ram.copy_from_slice(&initial_state[..ram_len]); + } else { + instance.ram[..len].copy_from_slice(&initial_state); + } + + instance } - pub fn start(&mut self) { + // Here is where you define the steps for assembling your custom Assembly language. + fn assemble(mut source: String) -> Vec { + let mut assembler: assembler::Assembler = assembler::Assembler::create(vec![ + assembler::Opcode::create("nop", 0), + assembler::Opcode::create("load", 1), + assembler::Opcode::create("store", 2), + assembler::Opcode::create("add", 3), + assembler::Opcode::create("sub", 4), + assembler::Opcode::create("jump", 5), + assembler::Opcode::create("jpiz", 6), + ]); + + assembler.assemble(&mut source) + } + + // This starts the CPU emulator. + fn start(&mut self) { loop { self.fetch_and_decode() } } +} +// These are the implementations specific to ExampleCPU +impl ExampleCPU { // This fetches the operands, based on the position of the execution_pointer, then runs the selected instruction. fn fetch_and_decode(&mut self) { self.operands[0] = self.ram[self.execution_pointer as usize]; @@ -81,7 +119,7 @@ impl ExampleCPU { } fn jpiz(&mut self) { - if self.operands[2] == 0 { + if self.registers[self.operands[2] as usize] == 0 { self.execution_pointer = self.operands[1]; } else { self.execution_pointer += 3; diff --git a/src/file.rs b/src/file.rs new file mode 100644 index 0000000..8873258 --- /dev/null +++ b/src/file.rs @@ -0,0 +1,21 @@ +use std::fs::File; +use std::io::{Read, Write}; + +pub fn load_file(file_path: &str) -> String { + let mut file: File = File::open(file_path).unwrap(); + let mut contents: String = String::new(); + let _ = file.read_to_string(&mut contents); + contents +} + +pub fn save_binary_u8(file_path: &str, content: Vec) { + let mut file: File = File::create(file_path).unwrap(); + file.write_all(&content).unwrap(); +} + +pub fn load_binary_u8(file_path: &str) -> Vec { + let mut file = File::open(file_path).unwrap(); + let mut buffer = Vec::new(); + file.read_to_end(&mut buffer).unwrap(); + buffer +} diff --git a/src/gui.rs b/src/gui.rs new file mode 100644 index 0000000..e69de29 diff --git a/src/main.rs b/src/main.rs index f0eec72..7623c5c 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,22 +1,47 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // Copyright (c) 2024 Patrick_Pluto +use clap::Parser; +use cpu::CPU; +use file::{load_binary_u8, load_file, save_binary_u8}; mod assembler; mod cpu; +mod file; + +/// SysForge: Systems programming made easy. +#[derive(Parser, Debug)] +#[command(version, about, long_about = None)] +struct Args { + /// Assemble a file + #[arg(short, long, default_value_t = false)] + assemble: bool, + + /// Run the emulator + #[arg(short, long, default_value_t = false)] + emulate: bool, + + /// Selects the file + #[arg(short, long, default_value = "main.asm")] + file: String, + + /// Selects the output file + #[arg(short, long, default_value = "main.out")] + output: String, + + /// Selects which CPU to use + #[arg(long, default_value = "ExampleCPU")] + cpu: String, +} fn main() { - let mut assembler: assembler::Assembler = assembler::Assembler::create(vec![ - assembler::Opcode::create("nop", 0), - assembler::Opcode::create("load", 1), - assembler::Opcode::create("store", 2), - assembler::Opcode::create("add", 3), - assembler::Opcode::create("sub", 4), - assembler::Opcode::create("jump", 5), - assembler::Opcode::create("jpiz", 6), - ]); - - let final_result: Vec = assembler.assemble(&mut "nop 0x00 0x22".to_string()); - dbg!(final_result); - let mut instance: cpu::ExampleCPU = cpu::ExampleCPU::create(false, [0; 256]); - instance.start(); + let args: Args = Args::parse(); + if args.assemble { + save_binary_u8( + &args.output, + cpu::ExampleCPU::assemble(load_file(&args.file)), + ); + } else if args.emulate { + cpu::ExampleCPU::create(true, load_binary_u8(&args.file)).start(); + } else { + } }